1. Field of the Invention
The present invention relates to semiconductor devices, a method of designing semiconductor devices, and recording media for storing semiconductor designing programs. In particular, the present invention relates to semiconductor devices having multilayer wiring structures, and a technique of designing a highly integrated semiconductor device having fine metal wires connected through via-contacts provided with extensions.
2. Description of the Related Art
Fine technology for semiconductor devices rapidly improving to provide very small circuit patterns. The very small circuit patterns have a problem.
The problem is an optical proximity-effect that occurs during a lithography process even if masks or steppers for producing circuit patterns are precise. The a proximity effects rounds an end of a metal wire. If the rounded wire end is connected to a via-contact, it reduces or eliminates a contact area between the wire end and the via-contact, to increases contact resistance between the wire and the via-contact and cause an open defect.
FIG. 1 is a plan view showing a pattern of metal wires designed according to a prior art. Wires 53 and 54 are in an upper layer and are connected to via-contacts 51 and 52, selectively. The via-contacts 51 and 52 are connected to wires 55 and 56 that are in a lower layer. FIG. 2 is a plan view showing metal wires manufactured according to the design of FIG. 1. FIG. 3 is a sectional view taken along a grid line V2 of FIG. 2. In FIGS. 1 and 2, the distance between adjacent grid lines indicates a minimum distance by which adjacent metal wires in each layer must be separated from each other. In FIG. 1, an end of each wire is square and is in contact with the whole surface of a via-contact. A mask formed according to the design of FIG. 1 also has a square shape for each wire end. During a lithography process, however, the optical proximity effect rounds each end of the wires 53 and 54 as shown in FIG. 2. The optical proximity effect may make the ends of the wires 53 and 54 recede in the arrow directions of FIG. 3, to reduce contact areas between the wires 53 and 54 and the via-contacts 51 and 52. In FIG. 3, dotted lines indicate designed ends of the wires 53 and 54.
There is an OPC (optical proximity correction) technique to increase a contact area between a metal wire end and a via-contact. This technique corrects wire ends when preparing data to make a mask. For example, this technique provides a wire end with a supplementary fringe that extends in every direction around a via-contact. FIG. 4 shows a pattern of metal wires having supplementary fringes 58 and 59 to cover via-contacts 51 and 52 according to a prior art. The pattern of FIG. 4 is useful to form metal wires having no round ends and having proper contact areas between the wire ends and via-contacts.
The supplementary fringes 58 and 59, however, increase the width of each wire at via-contact greater than the width of the other part of the wire. It is necessary, therefore, to separate the adjacent via-contacts 51 and 52 from each other with a grid line H2 interposing between them. In addition, other wires or via-contacts must not be arranged on grid lines that are adjacent to the via-contacts 51 and 52 or the intervals of grid lines must be increased to accommodate the supplementary fringes 58 and 59. These conditions deteriorate the integration of metal wires in a semiconductor device.
The supplementary fringes also increase the quantity of design data, extend a mask data preparation time, and elongate a semiconductor device development time.